1. Field of the Invention
The present invention relates to an information processing device and information processing method, and particularly relates to an information processing device and information processing method suitable for using in cases of converting the sampling rate or oversampled reception signals.
2. Description of the Related Art
Semiconductor devices have become smaller and finer in recent years, and digital circuits have become capable of realizing lower power consumption and high speeds, with a smaller installation area as well. On the other hand, analog circuits cannot be expected to have reduction in installation area like digital circuits, and property deterioration due to the effects of reduced power source voltage, transistor mismatches, and so forth, is unavoidable. From this perspective, there is a need to change functions which had been realized with analog circuits over to digital domain, i.e., a need to reduce analog signal processing units and replace these with digital signal processing units.
The primary functions of the digital domain of a receiver in wireless communication are frequency conversion, orthogonal modulation, channel selection, AGC (Automatic Gain Control), and so forth; changing these over to the digital domain in an effective manner requires an A/D converter with a high operating frequency and a wide dynamic range.
A direct conversion method using lowpass sigma-delta modulation has been proposed as a method for efficiently satisfying such demands (e.g., see Ville Eerola, et al, “Direct Conversion Using Lowpass Sigma-Delta Modulation”, ISCAS '92, pp 2653, 2656).
A known reception device 1 described therein will be described with reference to FIG. 1.
An input signal S(t) received by an unshown antenna is supplied to a bandpass filter (BPF) 11, subjected to band-limiting, and supplied to sigma-delta (ΣΔ) A/D converters 12-1 and 12-2.
The sigma-delta A/D converter 12-1 operates with a clock of the same frequency as the carrier wave frequency, and the sigma-delta A/D converter 12-2 operates with a clock having a phase difference of pi/2 as to the input clock of the sigma-delta A/D converter 12-1, each converting supplied RF signals into 1-bit bit strings and performing high order oversampling, thereby converting supplied analog signals into digital signals.
An LPF (Low pass filter) and decimation processing unit 13-1 which has received digital signals from the sigma-delta A/D converter 12-1 filters the supplied signals, performs decimation which is reducing the sampling rate of the supplied signal by a predetermined rate X1 (i.e., multiplies by 1/X1), and outputs an I-channel signal. An LPF (Low pass filter) and decimation processing unit 13-2 which has received digital signals from the sigma-delta A/D converter 12-2 performs filtering and decimation of the supplied signals, and outputs a Q-channel signal.
Examples of known methods with receivers using such conversion methods include performing analog processing such as filtering in discrete time domain so as to reduce the operating frequency of the sigma-delta converters (e.g., see K. Muhammad, et al, “A Discrete-Time Bluetooth Receiver in a 0.13 μm Digital CMOS Process”, ISSCC 2004, pp 268-269, and US 20030080888 A1, “Sigma-delta (ΣΔ) analog-to-digital converter (ADC) structure incorporating a direct sampling mixer”), arrangements using continuous time domain (e.g., see US 20040218693 A1, “Direct conversion delta-sigma receiver”), and so forth.
With the direct conversion method using sigma-delta modulation, channel selection filtering is realized primarily at the digital domain with very little attenuation of interfering waves being performed within the system bandwidth in the analog domain, so as to realize a fast sampling rate and wide dynamic range.
Also, quantization noise is added to the high-frequency component at the time of sigma-delta modulation, so there is the need for a filter for attenuation of quantization noise in the digital domain. Further, the sampling rate obtained from the output of the sigma-delta modulator is dependent on the channel frequency of the reception signals, and accordingly there is the need to convert to a frequency which the base band demands.
With the direct conversion method using sigma-delta modulation, these need to be realized in the digital domain, and also, there is the need for a flexible configuration regarding filtering and sampling rate conversion functions, in order to be able to handle various wireless systems.
In the case that the output bits of the sigma-delta modulator is 1-bit, there is a technique for realizing a FIR (Finite Impulse Response) filter and decimator without a multiplier, using memory and an adder and so forth (e.g., see U.S. Pat. No. 6,202,074 B1, “Multiplierless digital filtering”, and U.S. Pat. No. 6,584,157 B1, “Digital low pass filter”).
Next, a known example of a decimation filter outputting 1 bit will be described with reference to FIG. 2.
A 1-bit output series from an unshown sigma-delta modulator is input to an L-bit shift register 31, shifted by a timing of Fs, and 1 bit of serial signal is converted into N bits of parallel signals. An L-bit shift register 32 reads out the data of L bits at a timing of Fs/N, and based on each data, selects a positive or negative value for FIR tap coefficients (a1 or −a1, a2 or −a2, and so on) stored in memory 33, and the selected L tap coefficients are all added by an addition processing unit 34, thereby outputting signals that have been filtered and decimated.
With such a decimation filter, the 1 bit of input series only holds information for selecting whether the FIR filter tap coefficients are positive or negative. That is to say, storing information regarding whether the FIR tap coefficients are positive or negative in the memory 33 does away with the need for a multiplier.
Also, sigma-delta modulators generally have a great OSR (Over Sampling Ratio), so the sampling rate of output is very small as compared to the sampling rate of the input series. Accordingly, the speed demanded for addition processing normally is low.
The configuration of a digital block in IEEE 802.11g OFDM mode, to which the above-described decimation filter method has been applied, is as shown in FIG. 3, for example.
A SINC filter 51 executes moving-average computation. A decimator 52 reduces the sampling rate of the supplied signal by a predetermined rate X1 (i.e., multiplies by 1/X1), and in this case, multiples the sampling rate of the input signal by ½ and outputs. A ΣΔ A/D converter 53 converts the supplied RF signal into a bit stream of 1 bit, and performs high order oversampling. An LPF 54 filters high-frequency signals at or above a predetermined frequency band. A decimator 55 multiples the sampling rate of the input signals by 1/32 and outputs.
A sampling rate conversion unit (SRC) 56 converts the input signals having a sampling rate of Fs2 into output signals having a predetermined sampling rate of Fs3. An LPF 57 filters high-frequency components of a predetermined frequency band or higher. A decimator 58 multiples the sampling rate of the input signal by ½ and outputs.
In the case of using a 2412 MHz channel, the output frequency has been multiplied by ½ at the decimator 52 and multiplied by 1/32 at the decimator 55 and accordingly is 37.6875 MHz, so a sampling rate conversion unit 56 needs to convert this into an integer multiple of 20 MHz as demanded by a baseband chip which performs downstream processing, e.g., 40 MHz.
In the case of converting the sampling rate from 37.6875 MHz to 40 MHz for the frequency of the signals supplied to the sampling rate conversion unit 56, a method is normally employed wherein up-sampling is performed to a clock which realizes the lowest common multiple of the two clocks, passed through a filter for removing aliasing, and then down-sampling is performed (e.g., see P. P. Vaidyanathan, “Multirate systems and filter banks”, Prentice-Hall P T R).
FIG. 4 illustrates a further detailed configuration example of the sampling rate conversion unit 56.
An up-sampler 61 up-samples the frequency 37.6875 MHz of the signals supplied to the sampling rate conversion unit 56 640 times. An LPF 62 filters high-frequency signals at or above a predetermined frequency band to remove aliasing. A decimator 63 multiples the 24120 MHz signal frequency by 1/603 times to yield 40 MHz, which is then output.
Next, a different method for a sampling rate conversion unit will be described with reference to FIG. 5. Here, a sampling rate converter 71 which converts the frequency Fs of an input sample to 1.5 Fs will be described.
A resample processing unit 81 converts the frequency Fs of an input sample to 1.5 Fs. A CIC (Cascaded Integrator-Comb) filter is a filter which does not include a multiplier, with a comb filter which is a type of a FIR (Finite Impulse Response) being connected with a integrator which is a type of IIR (Infinite Impulse Response) in multiple stages. This filter is applicable to wideband signals, and exhibits steepness. A decimator 83 multiplies the frequency of the input signals by ½ and outputs.
Input/output of the resample processing unit 81 will be described with reference to FIG. 6. In the event of converting the frequency Fs of an input sample to 1.5 Fs, there is the need to output three samples as to two samples of signals input, so one sample of output needs to be interpolated with data of some sort. This means that with input signals shown in FIG. 7, aliasing is generated every 1.5 Fs×⅓=0.5 Fs frequency, as shown in FIG. 8. As shown in FIG. 6, using data of one timing earlier for the data to be inserted for interpolation allows aliasing signals to be attenuated, since this is equivalent to adding SINC filter properties (moving-average filter properties) to the aliasing signals generated. Further, output signals of a CIC filter 82 which is the addition average of every two samples of the 1.5 Fs signals can realize the SINC filter properties shown in FIG. 9, and accordingly can further attenuate aliasing components interfering at the time of decimation.
Symbols thus obtained are effected by aliasing if further subjected to ½ times decimation at the decimator 83. FIG. 10 shows the frequency properties of the output signals of the decimator 83. At this stage, aliasing signals are generated at 0.25 Fs and 0.5 Fs, but there is no program as long as the aliasing signals are attenuated to a permissible range at the SINC filter. Also, if the desired signal is a narrowband signal and aliasing signals do not interfere with the band, the effects thereof can be alleviated at a digital filter downstream.
Accordingly, as shown in FIG. 11, the decimation filter system shown in FIG. 5 is equivalent to having formed a two-stage SINC filter of SINC filters 91 and 92 between the resample processing unit 81 which performs 1.5 times up-sampling and the ½ times decimator 83, meaning that the implementation cost is very small.
A configuration example of a known digital block in IEEE 802.11g OFDM mode, to which the above-described sampling rate conversion method has been applied, is as shown in FIG. 12. Portions which correspond to those described with reference to FIGS. 3 and 5 are denoted with the same reference numerals, and description thereof will be omitted here.
With the arrangement in FIG. 12, in order to reduce implementation costs, the sampling rate of the output series of the upstream digital filter is set to 302 MHz using a ¼ times decimator 101, which is then input to the sampling rate conversion unit 71 including the resample processing unit 81 described with reference to FIG. 5. Interpolation processing is executed at the sampling rate conversion unit 71 using data of the previous timing, whereby the input 302 MHz signals are converted to 360 MHz and filtered, and the series thereof is subjected to 9-sample-addition and decimation at a decimator 102, so as to be output at 40 MHz. High-frequency component signals are filtered by the LPF 57 and the sampling rate of the input signals are multiplied by ½ at the decimator 58, thereby outputting signals of 20 MHz as demanded by the baseband chip.